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C HAPTER 1: D ESIGN F LOW
D ESIGN M ETHODOLOGIES AND P LANNING
After the initial or setup compilation, Altera recommends that you set the
Size to Fixed in order to yield better f MAX results. If device utilization is low,
increasing the size of the LogicLock region may allow the Fitter additional
flexibility in placement and may produce better final results.
When you perform an incremental compilation, the fitting and synthesis
results and settings for design partitions are saved in the project database.
For more information about assigning design partitions, refer to “Creating
Design Partitions” on page 57 in Chapter 4, “Constraint Entry.” For more
information about incremental compilation, refer to “Using Incremental
Compilation” on page 53 in Chapter 4, “Place and Route.”
f
For Information About
Using Quartus II incremental
compilation with LogicLock regions
Refer To
Quartus II Incremental Compilation for
Hierarchical & Team-Based Design chapter
in volume 1 of the Quartus II Handbook
“Module 7: Incremental Compilation” in the
Quartus II Interactive Tutorial
“About Incremental Compilation” in
Quartus II Help
A LTERA C ORPORATION
I NTRODUCTION TO THE Q UARTUS II S OFTWARE
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17
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相关PDF资料
SW-QUARTUS-SE-FLT SUBSCRIPTION FLOATALL REPL
SW006012 C COMPILER FOR DSPIC30F FAMILY
SW006013 C COMPILER MPLAB FOR DSPIC DSC
SW006015 C COMPILER MPLAB C32
SW300003-EVAL LIBRARY SOFT MODEM-EVAL ONLY
SW300010-EVAL SPEECH RECOG LIBRARY-EVAL ONLY
SW300040-EVAL LIBRARY NOISE SUPPR-EVAL ONLY
SW300060-EVAL LIBRARY ACOUSTIC ECHO-EVAL ONLY
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